How Huawei is going to dramatically increase the density of transistors without reducing the process technology.
Huawei has proposed its own replacement for Moore’s law, but the semiconductor industry has not yet received a new physical breakthrough, but a tricky way to bypass the technological gap. The company calls the Tau Scaling Law approach and promises a 1.4 nm-level transistor density by 2031, although an independent Omdia analyst considers the statement a strong marketing rather than a direct rival to future TSMC and Intel processes.
Huawei introduced a new approach at the IEEE International Symposium on Circuits and Systems 2026 in Shanghai. The report of New Semiconductor Path in Practice was made by He Tinbo, president of Huawei’s semiconductor business. He said Moore’s law gives less and less return, so the industry needs a different principle of developing electronic systems.
Moore’s law for decades described the growth in the number of transistors on a crystal and became a convenient formula for the entire industry: the fewer elements, the more computing power is placed on a chip. Huawei offers to shift attention from the geometric reduction of transistors during the signal inside the circuit. This approach was called Tau Scaling Law.
In a practical sense, Tau Scaling is reduced to the fight against delays in chains. The speed of operation of the chips is affected by the resistance and the parasitic capacity of transistors and connections between them, the length of data processing conveyors and the depth of logical circuits. The shorter the signal path and below the loss, the faster and more economical the chip works.
Huawei calls the new direction LogicFolding. The company is going to use such technology in the system on the Kirin 2026 crystal for smartphones. According to He Tinbo, LogicFolding is built on a free logical architecture and translates the diagram from one layer to two. In practice, transistors are placed not only next to each other, but also above each other.
Huawei claims that the previous density growth from 126 to 155 million transistors per square millimeter took three years, and LogicFolding in 2026 should raise the figure at once to 238 million transistors per square millimeter. The company connects the jump not with the usual reduction of transistors, but with a new layout of logic.
A similar direction is also studied by major competitors. Intel showed research on stack transistors and power on the back of the crystal, TSMC also speaks of the possibility of chips with trillions of transistors due to new packaging options and multi-layer architecture. Huawei is trying to move in the same direction, but in tougher conditions due to limited access to advanced lithographic technologies.
The most high-profile part of Huawei’s presentation concerns the forecast for 2031. The company claims that high-performance chips based on Taucaling Law will be able to get transistor density equivalent to the 14th-way process, or 1.4 nm. On paper, this indicator sounds like an application for the level of future advanced factories.
Omdia chief analyst Manoj Sukumaran considers the comparison incorrect. According to the expert, Huawei does not declare a real technology process of 1.4 nm and is still limited to the level of 7 nm. The growth of equivalent density is achieved by a hybrid connection of logical crystals and laying layers on each other. The projection area decreases, the density per square millimeter grows, but the transistors do not become as small as the present 1.4-nm process technology TSMC or Intel.
Intel plans to withdraw the 1.4 nm class 14A process in 2028, and mass production expects in 2029. TSMC moves in about the same time window. Against the background of these plans, Huawei’s statement does not look like a direct race on lithographs, but an attempt to compensate for the lag with packaging, architecture and a reduction in internal distances in the scheme.
Sukumaran admits that the claimed productivity gains of about 12.7% and energy efficiency by about 41% can be real. The analyst sees the source of improvements not in the new transistors, but in shorter connections and clock trees that distribute the clock signal along the crystal. The lack of details about leakage currents also speaks in favor of the version that the main effect is given by architecture, and not a physical reduction of elements.
For Huawei LogicFolding can become a working workable way under sanctions. The company is looking for ways to squeeze more from the available production capabilities, without waiting for access to the most advanced factory standards. But multi-layer packaging has a limit: each new layer complicates production, increases cost and gives less and less.
Huawei has proposed its own replacement for Moore’s law, but the semiconductor industry has not yet received a new physical breakthrough, but a tricky way to bypass the technological gap. The company calls the Tau Scaling Law approach and promises a 1.4 nm-level transistor density by 2031, although an independent Omdia analyst considers the statement a strong marketing rather than a direct rival to future TSMC and Intel processes.
Huawei introduced a new approach at the IEEE International Symposium on Circuits and Systems 2026 in Shanghai. The report of New Semiconductor Path in Practice was made by He Tinbo, president of Huawei’s semiconductor business. He said Moore’s law gives less and less return, so the industry needs a different principle of developing electronic systems.
Moore’s law for decades described the growth in the number of transistors on a crystal and became a convenient formula for the entire industry: the fewer elements, the more computing power is placed on a chip. Huawei offers to shift attention from the geometric reduction of transistors during the signal inside the circuit. This approach was called Tau Scaling Law.
In a practical sense, Tau Scaling is reduced to the fight against delays in chains. The speed of operation of the chips is affected by the resistance and the parasitic capacity of transistors and connections between them, the length of data processing conveyors and the depth of logical circuits. The shorter the signal path and below the loss, the faster and more economical the chip works.
Huawei calls the new direction LogicFolding. The company is going to use such technology in the system on the Kirin 2026 crystal for smartphones. According to He Tinbo, LogicFolding is built on a free logical architecture and translates the diagram from one layer to two. In practice, transistors are placed not only next to each other, but also above each other.
Huawei claims that the previous density growth from 126 to 155 million transistors per square millimeter took three years, and LogicFolding in 2026 should raise the figure at once to 238 million transistors per square millimeter. The company connects the jump not with the usual reduction of transistors, but with a new layout of logic.
A similar direction is also studied by major competitors. Intel showed research on stack transistors and power on the back of the crystal, TSMC also speaks of the possibility of chips with trillions of transistors due to new packaging options and multi-layer architecture. Huawei is trying to move in the same direction, but in tougher conditions due to limited access to advanced lithographic technologies.
The most high-profile part of Huawei’s presentation concerns the forecast for 2031. The company claims that high-performance chips based on Taucaling Law will be able to get transistor density equivalent to the 14th-way process, or 1.4 nm. On paper, this indicator sounds like an application for the level of future advanced factories.
Omdia chief analyst Manoj Sukumaran considers the comparison incorrect. According to the expert, Huawei does not declare a real technology process of 1.4 nm and is still limited to the level of 7 nm. The growth of equivalent density is achieved by a hybrid connection of logical crystals and laying layers on each other. The projection area decreases, the density per square millimeter grows, but the transistors do not become as small as the present 1.4-nm process technology TSMC or Intel.
Intel plans to withdraw the 1.4 nm class 14A process in 2028, and mass production expects in 2029. TSMC moves in about the same time window. Against the background of these plans, Huawei’s statement does not look like a direct race on lithographs, but an attempt to compensate for the lag with packaging, architecture and a reduction in internal distances in the scheme.
Sukumaran admits that the claimed productivity gains of about 12.7% and energy efficiency by about 41% can be real. The analyst sees the source of improvements not in the new transistors, but in shorter connections and clock trees that distribute the clock signal along the crystal. The lack of details about leakage currents also speaks in favor of the version that the main effect is given by architecture, and not a physical reduction of elements.
For Huawei LogicFolding can become a working workable way under sanctions. The company is looking for ways to squeeze more from the available production capabilities, without waiting for access to the most advanced factory standards. But multi-layer packaging has a limit: each new layer complicates production, increases cost and gives less and less.
